It is known in the prior art that individual active device regions in a semiconductor substrate may be separated from one another using a planar field oxide and a deep trench. Various field oxide isolation schemes have been proposed in the past, but many of these schemes have problems associated with "bird's beak" and "bird's head" formations. The "bird's beak" formation results from the lateral oxidation under the nitride masks used in the standard LOGOS (localized oxidation of silicon) procedure. The "bird's head" formation results from the lateral oxidation under the nitride masks used in the recessed or etch back LOCOS procedures. In fact, the walls of the recessed portions adjacent to the nitride masks, according to these procedures, greatly facilitate the lateral oxidation. These formations ("bird's beak" and "bird's head") encroach upon the active device area and thereby require greater distances between devices to compensate for this encroachment and result in a considerable reduction of packing density.
Various methods have been proposed to attempt the overcome this problem. One such method, referred to as "BOX", has been proposed by Kurosawa et al, "A New Bird's-Beak Free Field Isolation Technology for VLSI Devices", International Electron Devices Meeting, Dig. Tech. Paper, pp. 384-387 (1981). The name "BOX" has been given to this method because it involves burying oxide into etched grooves formed in silicon substrates. According to this method, the silicon substrate is etched in the field region using reactive ion etching (RIE) leaving a layer of aluminum covering the active device areas. Then, SiO.sub.2 is plasma deposited over the entire substrate. The SiO.sub.2 fills up the portion of the substrate previously etched away and also covers the aluminum layer.
The plasma-deposited silicon dioxide is subjected to a lift-off technique using buffered HF solution. This leaves V-shaped grooves in the periphery of the active region. The silicon dioxide on top of the aluminum mask is lifted off by etching. Then, the remaining V-shaped grooves are buried with silicon dioxide in a second step. This is accomplished by chemical vapor deposition (CVD) of silicon dioxide followed by a surface leveling technique using a spincoated resist. The resist and silicon dioxide layers are simultaneously etched by RIE. The oxide surfaces are then smoothed and any oxide remaining on the active device region must be removed by solution etching.
The problem with the BOX method is that it is too complex and cannot be performed efficiently and reliably. First of all, a two step oxide burying technique is needed, which is more time consuming than a single oxide deposition step. Furthermore, resist planarization and resist etch back steps are involved. These steps are difficult to control to close tolerances in a manufacturing environment. Resist planarization and etch-back techniques are not effective and are difficult to achieve for large active areas.
Another trench isolation method known in the prior art was disclosed in a publication by Rung et al, entitled, "Deep Trench Isolated CMOS Devices," International Electron Devices Meeting, Digest Technical Paper, pp. 237-240. According to this method, trenches are formed by RIE and are filled with silicon dioxide or poly-silicon deposited by using low pressure chemical vapor deposition (LPCVD). Once the trenches are filled, a critical etch back step must be accomplished using end point detection. After the etch back step, a capping oxidation step is performed using nitride as an oxidation mask.
Yet another method is disclosed by Katsumata et al., in "Sub-20 ps ECL Bipolar Technology with High Breakdown Voltage", ESSDERC (September 1993). In this paper, the authors disclose a shallow and deep trench isolation method using Low-Temperature Oxide Filling. According to this method, shallow and deep trenches are etched and then filled with liquid oxide deposition, a technique not yet fully established. A photoresist mask is then formed over the field areas and the exposed portions of the oxide layer are etched. Next, a second step of liquid oxide deposition is performed, followed by another etch back step. Hence, this process uses a critical alignment step and two liquid oxide deposition and etch back steps, all of which are not easily manufacturable. The above-mentioned problems with respect to large active areas apply here as well.